1. Field of the Invention
This invention relates to a flash memory device, and more particularly, to a flash memory device employing p-channel cells.
2. Description of the Prior Art
Conventional NAND-type floating gate flash memories are used in many non-volatile storage applications because they can be fabricated with a high density. In addition, they can operate at low-power and have high-speed page programming throughput.
FIG. 1 shows a conventional NAND floating gate flash memory using n-channel type memory cells. Each n-channel memory cell can be either a floating gate device or a silicon-oxide-nitride-oxide-silicon (SONOS) type device. Programming the conventional memory device may be performed by using positive Fowler-Nordheim (+FN) electron injection, where electrons are injected from an inversion channel into a floating gate or a nitride trapping layer of the memory cell. Conversely, erasing may be performed by negative Fowler-Nordheim (−FN) electron injection, where the electrons are injected from the floating gate into the channel. For example, a voltage of Vg=+18 volts is applied to a selected word line, e.g., WLN-1, which is connected to the gates of the n-channel memory cells marked A and B. A voltage of Vg=+10 is applied to all other (unselected) word lines (i.e., gates), including bit-line transistors (BLT) and source line transistors (SLT) of the memory device. The application of a positive gate voltage to all of the cells causes all of the MOSFET transistors in each NAND string of the conventional device to be turned-on, causing an inversion layer to formed that passes through the NAND strings. Referring again to FIG. 1, a first bit line (BL1) is set to a zero volt bias (i.e., VBL1=0V) or ground potential and therefore, the inversion layer in the cells connected to BL1 has a zero potential. However, a second bit line (BL2) is set to a positive voltage potential (i.e., VBL2=+8V), and therefore the inversion layer in the cells connected to BL2 is at a high potential.
Programming of a cell is accomplished by providing a large enough gate to source voltage in each cell to cause +FN injection to occur. Referring to FIG. 1, cell-A is selected by creating a large voltage drop across the cell. Specifically, since cell-A is connected to bit line BL1, which has a VBL1=0V and to word line WLN-1=+18V, a voltage drop of +18V is created across the cell. The +18V voltage drop provides for an efficient +FN injection, causing the voltage threshold in the cell to be raised to a higher programmed state (PV). Since cell-B is connected to bit line BL2 and to WLN-1, which are respectively biased at VBL2=+8V and WLN-1=+18V, a voltage drop of only +10V is created across cell-B. The +10V voltage drop is insufficient to cause +FN injection. Cell-C is connected to bit line BL1 and word line WL1, which are biased at VBL1=0V and WL1=+10V, thus creating a voltage drop of +10V across cell-C. Thus, any +FN effect is negligible for cell-C. Therefore, by the aforementioned method, individual cells may be programmed.
NAND n-channel floating gate flash memory devices are in widespread use. Many NAND flash memory devices are implemented with multi-level cell (MLC) technology which requires a more precise voltage threshold (Vt) distribution and control, thus require tighter control of process variables, than non-MLC applications. In addition, there is currently no known convergent +FN programming technique available for n-channel NAND floating gate flash memory devices. Further, due to the inter-floating gate structure of n-channel devices, there is a coupling effect between memory cells, thereby limiting the scaling of conventional NAND-type floating gate devices to greater densities.